Functional verification of the POWER5 microprocessor and POWER5 multiprocessor systems

POWER5 microprocessor and POWER5 multiprocessor systems D. W. Victor J. M. Ludden R. D. Peterson B. S. Nelson W. K. Sharp J. K. Hsu B.-L. Chu M. L. Behm R. M. Gott A. D. Romonosky S. R. Farago This paper describes the methods and simulation techniques used to verify the functional correctness and performance attributes of the IBM POWER5e microprocessor and the eServere p5 systems based on it. The approaches used were based on migrating the best practices that had been used to verify the POWER4e chip. The POWER5 chip design posed new challenges to the simulation team with the addition of simultaneous multithreading (SMT) and dynamic power management (DPM). In addition, there was further integration of cache and memory subsystem function onto the POWER5 chip. Since the design complexity had increased from the POWER4 design, the use of test plan coverage tools and techniques was expanded to ensure the maximum effectiveness of each simulation cycle run. A new toolset was also employed to improve the utilization of the large pool of computers used to run batch simulation jobs and to provide more efficient fail reproduction and bug fix management. For the system-level verification, a new test-case-generation tool was utilized which allowed for more targeted testing through a deeper knowledge of the system topology. In parallel with the mainline functional validation, verification of reliability functions and performance attributes also had increased focus for the POWER5 design.